1. Field of the Invention
This invention relates to high-density random access memory cells and in particular to a process for making such structures with a reduction in the number of mask steps compared to the prior art.
2. Prior Art
One prior art oxide isolation technology commonly used for manufacturing 16K RAMs employs thirteen masking steps to fabricate memory cells with active loads comprising lateral PNP transistors. These masking steps comprise the buried layer mask, the PNP base mask, the isolation mask, the self-aligned transistor mask, the base exclusion mask, the PNP emitter mask, the etch back mask, the NPN base mask, the contact mask, the first metal mask, the dielectric mask, the second metal mask, and the top side mask. One circuit constructed using this technology (a cross-coupled memory cell) is shown in FIG. 2. Resistors R1 and R2 comprise bypass resistors which are fabricated on the sidewalls of the cell by a P type field diffusion as taught in U.S. Pat. Nos. 4,118,728 and 4,149,177, the disclosures of which are hereby incorporated herein by reference. FIG. 1A illustrates (prior to the formation of electrical interconnects) in cross-section one-half of the cross-coupled memory cell illustrated in FIG. 2 (shown after the formation of electrical interconnects). In FIG. 1A transistor Q3 comprises a lateral transistor comprising P+ emitter 11, N type base 13 and P+ type collector 12. Collector 12 is connected by conductive side walls of P type conductivity (as taught by the '728 and '177 patents) to P+ contact region 18. Region 18 also provides an electrical contact to the base of transistor Q1. The impedance of this side wall comprises the resistor R1 and this P type sidewall is connected via regions 17, 18 and 19 to the P type base region 20 of multiple emitter transistor Q1. One emitter of transistor Q1 comprises N+ region 21 and a second emitter of transistor Q1 comprises N+ type region 24. The base region 20 is connected to additional base region 23 by means of P type material 22. Low resistivity N+ type buried interconnect region 14, among other functions, connects the N type collector regions 26 and 27. Base region 13 of lateral transistor Q3 is connected to the collector regions 26 and 27 of multiple emitter transistor Q1 by N+ buried interconnect region 14. Contact to region 14 is made via N type region 30 through N+ contact region 16. Oxide isolation regions 15a and 15b are formed over P+ type channel stop region 28a and 28 b formed in a conventional manner. The formation of oxide regions 15a and 15b is also well known in the semiconductor arts and thus will not be described in detail. Oxide isolation regions 15a and 15b actually form a single, annular isolation region when viewed from the top of the device and P+ channel stop regions 28a and 28b form a single, annular channel stop region beneath the annular oxide isolation region.
A plan view of the layout corresponding to the cell shown in cross-section in FIG. 1A is shown in top view in FIG. 1B. In FIG. 1B electrical contacts to the various transistors are identified by both the number of the transistor and the particular portion of the transistor contacted (a small e represents an emitter, a small b represents a base, and a small c represents a collector), as well as with the number of the corresponding regions of FIG. 1A. The structure shown in cross-section in FIG. 1A comprises one-half of the active devices of the cell of FIG. 2 with the other half being shown in top view to the right in FIG. 1B. Resistors R1 and R2 are shown as heavy bars in FIG. 1B. The wordline WL shown schematically in the top of FIG. 2 contacts the emitters of transistors Q3 and Q4 as shown in FIG. 1B. Resistor R1 connects the collector of lateral transistor Q3 to the base (contacted through base contact region 18 shown in FIG. 1A) of vertical transistor Q1 and thus to the collector of multiple emitter transistor Q2 through the topside metalization interconnect. The N type base of transistor Q3 is connected by means of a topside metal contact to the collector of transistor Q4 and by means of P type sidewall resistor R2 to the base of multiple emitter transistor Q2. Emitter e1 of Q2 (FIG. 1B) is connected to the word line WL and emitter e2 of Q2 is connected to the bit line BL, which is the complement of the bit line BL. Likewise, the emitter e1 of transistor Q1 is connected to the word line WL and the emitter e2 of transistor Q1 is connected to the bit line BL. Resistor R1 connects the collector of transistor Q3 to the base of transistor Q1 by means of resistive sidewall conductive paths passing beside the N type epitaxial layer 30 (FIG. 1A) and insulated therefrom by a PN isolation junction and making contact to the base 20, 23 of NPN transistor Q1 through P type region 17, P+ type region 18 and P type region 19. The base region 20, 23 of Q1 is connected by means of a conductive layer on top of the circuit to the collector of Q2 and the base of lateral transistor Q4 (FIG. 1B).
The structure described above is one manufactured in the prior art by Fairchild Camera and Instrument Corporation and typically provides a memory cell of approximately one (1) sq. mil. While this cell represents the state of the art of bipolar technology, it still is not small enough to yield devices with a packing density required to make very large scale integrated circuits (VLSI structures).